Layout Time!!

The exciting part is nearly here. There are only three more geometries to be made and verified and then layout begins. There are going to be a lot of traces to lay. I am shooting for a 4 layer board. After reviewing the dimensions of everything it seems that Advanced Circuits may be able to make boards for us after all.  Not much other news than that.

Parts

Well, progress has been going well on the design even though progress on the blg stopped temporarily. I have finished schematic capture. I am now going through my BOM downloading all of the datasheets, verifying part selection and creating needed geometries. However much fun all of that sounds I am looking forward to the layout process for this board. We have found that the Analog Devices reference board uses a 6mil drill for some of their vias. Our normal circuit board manufacturer, Advanced Circuits, can’t do that small of drill hole in their normal boards. We may have to search for someone else to produce the PCB if we can’t figure out a way around this.

Power

As far as schematic work goes I spent most of the day working on the power supply design. I also went through and finished the audio codec schematic and researched the reset circuitry.

I also spent part of the day familiarizing myself with the kernel source tarball that I downloaded.

JTAG

The ~TRST pin for JTAG emulation is not currently implemented on our JTAG dongle as CPLDs and FPGAs do no use this pin. Unfortunately, the ~TRST pin is supposed to be pulled low while the JTAG interface is not in use and is supposed to be pulled high when the JTAG interface is in use. For this reason pin 4 of the 10-pin programming dongle will be tied to Vcc of the board (pin 2) through a 3.3K resistor. On the board side, ~TRST will be pulled low by a 47K resistor.

Beyond learning about the JTAG standard and finishing the implementation of JTAG on the board I also finished the SPI interface and most of the audio codec. I need to finish drawing the power supply, the RS232 interface and the connectors and then go through and verify the entire design.

SPI and Codecs

Today was mostly spent going through and verifying little peices of the design as they were put into the schematic. I e-mailed the guy creating the KEDO audio codec to see if I could find out a little more about how he designed his interface. I also moved the flash memory over to an SPI part to save on board clutter and asynchronous memory space. This was also necessary as it was looking like 2MB would probably have not been enough to support our code requirements. The SPI wil be routed through the CPLD to make it so that we can use the Cypress chip to USB program the memory for initial boot up.

Move to BF537

Major Design Change! We moved to the BF537 part. It is compatible with all components of the curent design but adds features such as 802.3 MAC, CAN, TWI (I2C) along with more timers and GPIO. It will also make interfacing with the audio codec easier. My part generator cranked almost a second to spit out the 208 pin part, but it’s done and I am progressing on schematic capture.

Schematic Capture

Plugging away at schematic capture. I hope to be done by the end fo the day Thursday. I have stopped for a little while to work on researching the audio codec interface. Hopefully I can finish figuring that out tonight or tomorrow morning.

Auto Part Generation Success!

Here is a picture of the Blackfin made using my auto-part generation for PADS PowerLogic from .csv files using Ruby scripts. (the part has not been modified at all, this is exactly how the auto part gen created it) I need to clean up the code a little and make a good fron end for it, but this tool has already saved me a lot of time. Hopefully schematic capture will be finished soon. If you have interest in this code e-mail me.