Codec Change

Well, it turns out that cheap isn’t always good. We chose to change the audio codec on the board because it required that we generate three external clocks to feed into it. This used an unjustifiable amount of board resources and also would have required us to change the crystal for the main processor which would have made it harder to implement ethernet in the future. For this reason, the UDA1345TS is out and we have settled on an AC97 codec from analog devices. The new part number is AD1981BL. This codec also has mic and headphone preamps built into it.

Kernel Booting … Done

The kernel boots! We now have the kernel booting out of flash. It then mounts the JFFS2 from the Dataflash chip and proceeds to boot. Not too much can be done with the current image but all of the files are there and we were able to play a quick game of dungeon on the serial terminal. The next big task is to get the audio driver done. There are files in the kernel for the uda1341 chipset which is similar to our uda1345 chipset. Unfortunately this file seems to be a remnant of a driver from the 2.4 kernel and not of the necessary files exist to get it working. Due to this we are starting from one of the ADI chips that has a driver to use the SPORT on the blackfin in I2S mode and then rewriting the parts of the functions that are chip specific. We hope to have a first shot at the driver early next week.

Booting in multiple ways

It’s been a little while since I last posted but a lot has happened. We have now successfully run u-boot in both UART boot and SPI boot modes. Tim Louden managed to quickly get together a flash driver for our spi chip that allows us to interface it with u-boot. Now the real work begins. The kernel itself. We found that the version of the toolchain that we were using was not compatible with the version of the kernel that we were using so we reverted back to the most recent release of the kernel rather than the svn version. This is currently being worked into the repository and hopefully linux hacking can begin tomorrow. Once we get the kernel booting the next big task is to see if we can get the audio codec to respond.

Power

As far as schematic work goes I spent most of the day working on the power supply design. I also went through and finished the audio codec schematic and researched the reset circuitry.

I also spent part of the day familiarizing myself with the kernel source tarball that I downloaded.

SPI and Codecs

Today was mostly spent going through and verifying little peices of the design as they were put into the schematic. I e-mailed the guy creating the KEDO audio codec to see if I could find out a little more about how he designed his interface. I also moved the flash memory over to an SPI part to save on board clutter and asynchronous memory space. This was also necessary as it was looking like 2MB would probably have not been enough to support our code requirements. The SPI wil be routed through the CPLD to make it so that we can use the Cypress chip to USB program the memory for initial boot up.

Move to BF537

Major Design Change! We moved to the BF537 part. It is compatible with all components of the curent design but adds features such as 802.3 MAC, CAN, TWI (I2C) along with more timers and GPIO. It will also make interfacing with the audio codec easier. My part generator cranked almost a second to spit out the 208 pin part, but it’s done and I am progressing on schematic capture.

Schematic Capture

Plugging away at schematic capture. I hope to be done by the end fo the day Thursday. I have stopped for a little while to work on researching the audio codec interface. Hopefully I can finish figuring that out tonight or tomorrow morning.

Meeting 08/24/2006

Minutes from meeting with Don Heer:

• PCB Layout Software:
  • Continue to use PADS
  • BGA pins will be named with numbers (i.e. 1001 for A1 and 2011 for B11).

• USB:
  • Move from FTDI to Cypress CY8C24794 and add programming functionality
  • Connect JTAG Pins to Cypress Chip for USB programming
  • Cypress chip also allows some extra analog inputs

• Memory:
  • Go ahead with single chip for memory.
  • Saves board space.
  • Cheaper.
  • Less flexibility for future memory upgrades.

• Audio Codec:
  • Proceed with cheaper codec.
  • This requires changing the system clock to 12.288MHz.
  • Need to decide between static and serial configuration.

• CPLD
  • Use the faster 7ns part to accomadate the system bus speed.

Other Items:

• Find price of Blackfin Handy Board

Audio Codecs & Price Cuts

I am discovering how to make the newly selectec UDA1345TS audio codec connect to the BF533. I am beginning to think that a static configuration rather than serial configuration will be the easiest to implement. Changing to this codec has shaved signifigant cost off of the board. The price is around $44 now instead of $54. There have been issues with the PADs software that has kept me from progressing further on the schematic. I will talk to Don about this tomorrow. It may be best to leave this design in board station for now. I also discovered that the speed grade of the CPLD that I had selected was too small to operate at the same speed as the SDRAM. We need the 7ns version rather than the 10ns version so that we can reach 120MHz operating speeds.

I also found this board. Unfortunately, there are not schematics. They seem to have got a lot of support from Analog Devices through.