JTAG

The ~TRST pin for JTAG emulation is not currently implemented on our JTAG dongle as CPLDs and FPGAs do no use this pin. Unfortunately, the ~TRST pin is supposed to be pulled low while the JTAG interface is not in use and is supposed to be pulled high when the JTAG interface is in use. For this reason pin 4 of the 10-pin programming dongle will be tied to Vcc of the board (pin 2) through a 3.3K resistor. On the board side, ~TRST will be pulled low by a 47K resistor.

Beyond learning about the JTAG standard and finishing the implementation of JTAG on the board I also finished the SPI interface and most of the audio codec. I need to finish drawing the power supply, the RS232 interface and the connectors and then go through and verify the entire design.

SPI and Codecs

Today was mostly spent going through and verifying little peices of the design as they were put into the schematic. I e-mailed the guy creating the KEDO audio codec to see if I could find out a little more about how he designed his interface. I also moved the flash memory over to an SPI part to save on board clutter and asynchronous memory space. This was also necessary as it was looking like 2MB would probably have not been enough to support our code requirements. The SPI wil be routed through the CPLD to make it so that we can use the Cypress chip to USB program the memory for initial boot up.

How to put a part in a computer

Since many of the design questions were cleared up early today I started to move ahead with schematic capture. I was able to get the ez-kit lite files from analog and the board was routed in PowerPCB which allowed me to look at their design and capture their geometries. An image of the board can be seen above. Unfortunately, I was not able to access their schematic symbols which is why I downloaded the files in the first place.

I looked around the internet for ways to get the existing schematic symbols from the ucLinux team or from Analog to convert into PowerLogic, but I couldn’t find a way. I did run across a tool for generating parts using excel files that looks promising. Unfortunately, the tool does not seem to be free. I e-mailed the company to inquire about licensing. I may just need to write my own tool or figure out how to input symbols faster.

I also pursued information on the handyboard and found that they will be releasing schematics in the fall. Their board is going to cost nearly $600 dollars a tad bit more than our $45 board. Their schematics may be useful in design when they come out, but we should have prototypes out by then.

I think that we may be able to make the board useful for both one and two chip memory configurations by swizzling some wires, I am still investigating this though.

I am also still looking into the USB design. We may be able to add more features since we have switched to the cypress chip. I need to investigate how to hook the cypress chip to the CPLD and the JTAG port on the Blackfin.

Meeting 08/24/2006

Minutes from meeting with Don Heer:

• PCB Layout Software:
  • Continue to use PADS
  • BGA pins will be named with numbers (i.e. 1001 for A1 and 2011 for B11).

• USB:
  • Move from FTDI to Cypress CY8C24794 and add programming functionality
  • Connect JTAG Pins to Cypress Chip for USB programming
  • Cypress chip also allows some extra analog inputs

• Memory:
  • Go ahead with single chip for memory.
  • Saves board space.
  • Cheaper.
  • Less flexibility for future memory upgrades.

• Audio Codec:
  • Proceed with cheaper codec.
  • This requires changing the system clock to 12.288MHz.
  • Need to decide between static and serial configuration.

• CPLD
  • Use the faster 7ns part to accomadate the system bus speed.

Other Items:

• Find price of Blackfin Handy Board

Audio Codecs & Price Cuts

I am discovering how to make the newly selectec UDA1345TS audio codec connect to the BF533. I am beginning to think that a static configuration rather than serial configuration will be the easiest to implement. Changing to this codec has shaved signifigant cost off of the board. The price is around $44 now instead of $54. There have been issues with the PADs software that has kept me from progressing further on the schematic. I will talk to Don about this tomorrow. It may be best to leave this design in board station for now. I also discovered that the speed grade of the CPLD that I had selected was too small to operate at the same speed as the SDRAM. We need the 7ns version rather than the 10ns version so that we can reach 120MHz operating speeds.

I also found this board. Unfortunately, there are not schematics. They seem to have got a lot of support from Analog Devices through.